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PRELIMINARY
Am486(R) DX4 3-Volt Processor
High-Performance, Clock-Selectable, 3.3 V, 32-Bit Microprocessor
DISTINCTIVE CHARACTERISTICS
Operating voltage range 3.3 V 0.3 V -- 120-MHz operating frequency uses a 40-MHz external bus -- 100-MHz operating frequency uses a 33-MHz external bus -- Wide range of chipsets and support available through the AMD FusionPCSM Program High Integration On-Chip -- 8-Kbyte code and data cache -- Floating-point unit -- Paged, virtual memory management High-Performance Design -- -- -- -- -- Frequent instructions execute in one clock 105.6-Million bytes/second burst bus at 33 MHz 128-Million bytes/second burst bus at 40 MHz 0.5-micron CMOS process technology Dynamic bus sizing for 8, 16, and 32-bit buses Complete 32-Bit Architecture -- Address and data buses -- All registers -- 8, 16, and 32-bit data types Multiprocessor Support -- Multiprocessor instructions -- Cache consistency protocols -- Support for second-level cache Standard 168-Pin PGA Package
Advanced Micro Devices
Supports Environmental Protection Agency's (EPA) "Energy Star" program -- Energy management capability provides excellent base for energy-efficient design -- Works with a variety of energy efficient, power managed devices
GENERAL DESCRIPTION
The AM486DX4 microprocessor is a high-performance 486 desktop solution that provides optimal price/performance for high-end 486 power-managed systems. The AM486DX4 CPU offers superior local bus graphics performance for Microsoft(R) Windows(R). Using AMD's speed-multiplying technology, the AM486DX4 CPU and cache operate two to three times faster than the external memory bus. It is manufactured using AMD's new 3.3-V CMOS process technology to consume about 2.6 watts of power at 100 MHz or 3.2 watts at 120 MHz. This 3.3-V technology provides superior solutions for low-power EPA's Energy Star Green PCs and portables. The AM486DX4 processor operates with a 1X clock input. This 1X clock simplifies system design by reducing the clock frequency required by external devices. The 1X clock also reduces RF emission and simplifies clock generation. The input signal is doubled or tripled internally to achieve the maximum 2X or 3X operating frequency. The phases of the core clock are controlled by an internal Phase Lock Loop (PLL) circuit.
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication#19160 Rev: D Amendment/0 Issue Date: July 1995
AMD
PRELIMINARY
BLOCK DIAGRAM
Am486 CPU Pipelined 32-Bit Microarchitecture
VOLDET
64-Bit Interunit Transfer Bus 32-Bit Data Bus 32 32-Bit Data Bus 32 Linear Address Bus Base/ Index Bus 32 ALU 32 PCD, PWT Segmentation Unit Descriptor Registers Limit and Attribute PLA 2 Paging Unit 20 Physical Address 8-Kbyte Cache Cache Unit 32 32 Core Clock
Power Planes
VCC, VSS
CLKMUL
Clock Multiplier
CLK
Barrel Shifter Register File
Address Drivers
Bus Interface A31-A2, BE3-BE0
Write Buffers 4 x 80 Data Bus Transceivers D31-D0 ADS, W/R, D/C, M/IO, PCD, PWT, RDY, LOCK, PLOCK, BOFF, A20M, BREQ, HOLD, HLDA, RESET, INTR, NMI, FERR, IGNNE, UP
Translation Lookaside Buffer
32 128 Bus Control Request Sequencer
Micro-instruction
Displacement Bus 32 Code Stream
Prefetcher 32-byte Code Queue 2 x 16 bytes
FloatingPoint Unit FloatingPoint Register File
Central and Protection Test Unit Decoded Instruction Path
Burst Bus Control Bus Size Control Cache Control Parity Generation and Control Boundary Scan Control
BRDY, BLAST BS16, BS8 KEN, FLUSH, AHOLD, EADS PCHK, DP3-DP0 TDI, TDO TMS, TCK
Instruction Decode
24
Control ROM
19160C-001
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AM486DX4 Microprocessor
PRELIMINARY
AMD
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
A
80486DX4
-120
N
V
8
T CACHE TYPE T = Write-Through CACHE SIZE 8 = 8 Kbytes VOLTAGE V = 3.3 Volt Core, 5 V Tolerant I/O ICE MICROCODE Blank = Contains ICE Microcode N = No ICE Microcode SPEED OPTION -120 = 120 MHz -100 = 100 MHz DEVICE NUMBER/DESCRIPTION 80486DX4 AM486DX4 High-Performance, Clock-Selectable, 32-Bit Microprocessor PACKAGE TYPE A = 168-Pin PGA (Pin Grid Array)
Valid Combinations A 80486DX4 -120NV8T -100NV8T
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
AM486DX4 Microprocessor
3
AMD
PRELIMINARY
CONNECTION DIAGRAMS AM486DX4 CPU Pin Side View
168-Pin PGA (Pin Grid Array) Package
1
A27
2
A26 A25 VSS A29 D1 VCC D6 VCC D5 D3 VCC D8 VCC D13 D18 D21 D22
3
4
5
6
VSS VCC A24
7
A12 A15 A22
8
VSS VCC A20
9
VSS VCC A16
10
VSS VCC A13
11
VSS VCC A9
12
VSS A11 A5
13
A10 A8 A7
14
VSS VCC A2
15
A6
16
A4
17
ADS
A23 VOLDET A14 VCC A17 A30 DP0 D4 D7 D14 D16 DP2 D12 D15 D10 D17 CLK VSS TCK VCC VSS D23 VCC VSS DP3 VSS A19 A18 A21
S
A28 A3 BLAST NC
S R
A31 BREQ PLOCK PCHK
R Q
D0 HLDA LOCK D/C VCC M/IO VCC VCC VCC BE1 VCC VCC RDY VCC BS8 VSS
Q P
D2 W/R
P N
VSS VSS
N M
VSS PWT BE0 BE2 BRDY NC KEN HOLD A20M D27 D25 D24 D26 VCC VSS D28 D31 D29 D30 VCC VSS NC NC NC UP VCC VSS NC NC VSS
M L
VSS VSS
L K
INC PCD
K J
VSS VSS
J H
VSS VSS
H G
DP1 BE3
G F
VSS VSS
F E
D9 BOFF
E D
D11 FERR FLUSH RESET BS16
D C
D19 NC CLKMUL TMS NC NC NMI TDO EADS
C B
D20 TDI IGNNE INTR AHOLD
B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
A
Note: NC = No connect. To guarantee functionality with future revisions, these pins must not be connected.
19160c-002
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AM486DX4 Microprocessor
PRELIMINARY
AMD
CONNECTION DIAGRAMS AM486DX4 CPU Top Side View
168-Pin PGA (Pin Grid Array) Package
17
ADS
16
A4
15
A6
14
VSS VCC A2
13
A10 A8 A7
12
VSS A11 A5
11
VSS VCC A9
10
VSS VCC A13
9
VSS VCC A16
8
VSS VCC A20
7
A12 A15 A22
6
VSS VCC A24
5
4
3
2
A26 A25 VSS A29 D1 VCC D6 VCC D5 D3 VCC D8 VCC D13 D18 D21 D22
1
A27
A14 VOLDET A23 A18 A21 VSS A19 VCC A17
S
NC BLAST A3 A28
S R
PCHK PLOCK BREQ A31
R Q
VSS VCC M/IO VCC VCC VCC BE1 HLDA A30 DP0 D4 D7 D14 D16 DP2 D12 D15 D10 D17 NC UP VCC VSS NC NC NC D30 VCC VSS D28 D31 D29 D26 VCC VSS D27 D25 D24 VCC VSS DP3 VCC VSS D23 CLK VSS TCK D0
Q P
W/R LOCK D/C D2
P N
VSS VSS
N M
VSS PWT BE0 BE2 VSS
M L
VSS VSS
L K
PCD INC
K J
VSS VCC BRDY VCC RDY NC KEN VSS
J H
VSS VSS
H G
BE3 DP1
G F
VSS VCC HOLD BS8 A20M VSS
F E
BOFF D9
E D
BS16 RESET FLUSH FERR NC D11
D C
EADS TDO NMI TMS CLKMUL NC TDI NC NC D19
C B
AHOLD INTR IGNNE D20
B A 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
19160c-003
Note: NC = No connect. To guarantee functionality with future revisions, these pins must not be connected.
AM486DX4 Microprocessor
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AMD
PRELIMINARY
PIN DESIGNATIONS (Functional Grouping)
Address Pin Name A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pin No. Q-14 R-15 S-16 Q-12 S-15 Q-13 R-13 Q-11 S-13 R-12 S-7 Q-10 S-5 R-7 Q-9 Q-3 R-5 Q-4 Q-8 Q-5 Q-7 S-3 Q-6 R-2 S-2 S-1 R-1 P-2 P-3 Q-1 Data Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Pin No. P-1 N-2 N-1 H-2 M-3 J-2 L-2 L-3 F-2 D-1 E-3 C-1 G-3 D-2 K-3 F-3 J-3 D-3 C-2 B-1 A-1 B-2 A-2 A-4 A-6 B-6 C-7 C-6 C-8 A-8 C-9 B-8 Control Pin Name A20M ADS AHOLD BE0 BE1 BE2 BE3 BLAST BOFF BRDY BREQ BS8 BS16 CLK CLKMUL D/C DP0 DP1 DP2 DP3 EADS FERR FLUSH HLDA HOLD IGNNE INTR KEN LOCK M/IO NMI PCD PCHK PLOCK PWT RDY RESET UP VOLDET W/R Pin No. D-15 S-17 A-17 K-15 J-16 J-15 F-17 R-16 D-17 H-15 Q-15 D-16 C-17 C-3 B-13 M-15 N-3 F-1 H-3 A-5 B-17 C-14 C-15 P-15 E-15 A-15 A-16 F-15 N-15 N-16 B-15 J-17 Q-17 Q-16 L-15 F-16 C-16 C-11 S-4 N-17 Pin Name TCK TDI TDO TMS Test Pin No. A-3 A-14 B-16 B-14 INC/NC Pin No. A-10 A-12 A-13 B-10 B-12 C-10 C-12 C-13 G-15 J-1 R-17 VCC Pin No. B-7 B-9 B-11 C-4 C-5 E-2 E-16 G-2 G-16 H-16 K-2 K-16 L-16 M-2 M-16 P-16 R-3 R-6 R-8 R-9 R-10 R-11 R-14 VSS Pin No. A-7 A-9 A-11 B-3 B-4 B-5 E-1 E-17 G-1 G-17 H-1 H-17 K-1 K-17 L-1 L-17 M-1 M-17 P-17 Q-2 R-4 S-6 S-8 S-9 S-10 S-11 S-12 S-14
Notes: INC = Internal No Connect (J-1). NC = No Connect (A-10, A-12, A-13, B-10, B-12, C-10, C-12, C-13, G-15, R-17). VOLDET is connected internally to VSS.
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AM486DX4 Microprocessor
PRELIMINARY
AMD
LOGIC SYMBOL
Clock Address Mask Clock Multiplier
28 2
CLK A20M CLKMUL A31-A4 A3-A2 BE3-BE0
VOLDET
D31-D0
32
Data Bus
DP3-DP0 PCHK
4
Data Parity
Address Bus
4
BRDY BS8 Bus Cycle Control BS16 ADS RDY BLAST
Burst Control
Am486 CPU
PWT PCD
Page Cacheability
M/IO D/C Bus Cycle Definition W/R LOCK PLOCK
UP
Upgrade Processor Present
KEN FLUSH AHOLD EADS
Interrupts
INTR NMI RESET
Cache Control/ Invalidation
HOLD BOFF BREQ HLDA
TCK IGNNE FERR TMS
TDI TDO
17852B-114
Bus Arbitration
Numeric Error Reporting
IEEE Test Access Port
AM486DX4 Microprocessor
7
AMD
PRELIMINARY The AM486DX4 processor provides four special bus cycles to indicate that certain instructions have been executed, or certain conditions have occurred internally. The special bus cycles (in Table 1) are defined when the bus cycle definition pins are in the following state: M/IO=0, D/C=0, and W/R=1. During these cycles the address bus is driven Low while the data bus is undefined. The external hardware must acknowledge these special bus cycles by returning RDY and BRDY.
-------------------------------------------------------------- --------------------------------------------------------------
PIN DESCRIPTIONS
The following paragraphs define the AM486DX4 CPU pins (signals).
A31-A4/A3-A2
Address Lines (Inputs/Outputs)/(Outputs) A31-A2, together with the byte enables BE3-BE0, define the physical area of memory or input/output space accessed. Address lines A31-A4 are used to drive addresses into the microprocessor to perform cache line invalidations. Input signals must meet setup and hold times, t22 and t23. A31-A2 are not driven during bus or address hold.
Table 1 . Special Bus Cycle Encoding
BE3 1 1 1 0 BE2 1 1 0 1 BE1 1 0 1 1 BE0 0 1 1 1 Special Bus Cycles Shutdown Flush Halt Write Back
A20M
Address Bit 20 Mask (Active Low; Input) When asserted, the AM486DX4 microprocessor masks physical address bit 20 (A20) before performing a lookup to the internal cache or driving a memory cycle on the bus. A20M emulates the address wraparound at 1 Mbyte, which occurs on the 8086. A20M is active Low and should be asserted only when the processor is in Real Mode. This pin is asynchronous but should meet setup and hold times, t20 and t21, for recognition in any specific clock. For proper operation, A20M should be sampled High at the falling edge of RESET.
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BS8/BS16
Bus Size 8 (Active Low; Input)/ Bus Size 16 (Active Low; Input) These pins cause the AM486DX4 microprocessor to run multiple bus cycles to complete a request from devices that cannot provide or accept 32 bits of data in a single cycle. The bus sizing pins are sampled every clock. The state of these pins in the clock before RDY is used by the AM486DX4 microprocessor to determine the bus size. These signals are active Low and are provided with internal pull-up resistors. These inputs must satisfy setup and hold times, t14 and t15, for proper operation.
ADS
Address Status (Active Low; Output) ADS indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS is driven active in the same clock as the addresses are driven. ADS is active Low and is not driven during bus hold.
BLAST
Burst Last (Active Low; Output) BLAST indicates that the next time BRDY is returned, then the burst bus cycle is complete. BLAST is active for both burst and non-burst bus cycles. BLAST is active Low and is not driven during bus hold.
AHOLD
Address Hold (Active High; Input) This request allows another bus master access to the AM486DX4 microprocessor's address bus for a cache invalidation cycle. The AM486DX4 microprocessor stops driving its address bus in the clock following AHOLD going active. Only the address bus is floated during address hold; the remainder of the bus remains active. AHOLD is active High and is provided with a small internal pull-down resistor. For proper operation, AHOLD must meet setup and hold times, t18 and t19.
BOFF
Backoff (Active Low; Input) This input pin forces the AM486DX4 microprocessor to float its bus in the next clock. The microprocessor floats all pins normally floated during bus hold, but HLDA is not asserted in response to BOFF. BOFF has higher priority than RDY or BRDY; if both are returned in the same clock, BOFF takes effect. The microprocessor remains in bus hold until BOFF is negated. If a bus cycle is in progress when BOFF is asserted, the cycle is restarted. BOFF is active Low and must meet setup and hold times, t18a and t19, for proper operation.
BE3-BE0
Byte Enables (Active Low; Outputs) These pins indicate active bytes during read and write cycles. During the first cycle of a cache fill, the external system should assume that all byte enables are active. BE3 applies to D31-D24, BE2 applies to D23-D16, BE1 applies to D15-D8, and BE0 applies to D7-D0. BE3- BE0 are active Low and are not driven during bus hold.
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AM486DX4 Microprocessor
PRELIMINARY
AMD
BRDY
Burst Ready Input (Active Low; Input) This input pin performs the same cycle during a burst cycle that RDY performs during a non-burst cycle. BRDY indicates that the external system has presented valid data in response to a read or that the external system has accepted data in response to write. BRDY is ignored when the bus is idle and at the end of the first clock in a bus cycle. BRDY is sampled in the second and subsequent clocks of a burst cycle. The data presented on the data bus is strobed into the microprocessor when BRDY is sampled active. If RDY is returned simultaneously with BRDY, BRDY is ignored and the burst cycle is prematurely aborted. BRDY is active Low and is provided with a small pull-up resistor. BRDY must satisfy the setup and hold times, t16 and t17.
D/C, M/IO, W/R
Data/Control, Memory/Input/Output, Write/Read (Active High/Active Low; Output) These are the primary bus definition signals (in Table 2). These signal are driven valid as the ADS signal is asserted. The bus definition signals are not driven during bus hold and follow the timing of the address bus. The D/C bus cycle definition pin distinguishes memory and I/O data cycles (D) from the control cycles (C): interrupt acknowledge, halt, and instruction fetching. The M/IO bus cycle definition pin distinguishes memory cycles (M) from input/output cycles (IO). The W/R bus definition pin distinguishes write cycles from read cycles.
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Table 2. Bus Cycle Definition
BREQ
Internal Cycle Pending (Active High; Output) BREQ indicates that the AM486DX4 microprocessor has internally generated a bus request. BREQ is generated whether or not the AM486DX4 microprocessor is driving the bus. BREQ is active High and is never floated, except for three-state test mode (see FLUSH).
M/IO 0 0 0 0 1 1 1 1 D/C 0 0 1 1 0 0 1 1 W/R 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge Halt/Special Cycle I/O Read I/O Write Code Read Reserved Memory Read Memory Write
CLK
Clock (Input) CLK is a 1X clock providing the fundamental timing for the bus interface unit and is multiplied in accordance with the CLKMUL pin to provide the internal frequency for the AM486DX4 microprocessor. All external timing parameters are specified with respect to the rising edge of CLK.
-------------------------------------------------------------- --------------------------------------------------------------
DP3-DP0
Data Parity (Active High; Inputs/Outputs) Data parity is generated on all write data cycles using the same timing as the data lines. Even parity information must be driven back into the microprocessor on the data parity pins with the same timing as read information. This process ensures that the correct parity check status is indicated. The signals read on these pins do not affect program execution. Input signals must meet setup and hold times, t22 and t23. DP3-DP0 should be connected to VCC through a pull-up resistor in systems not using parity. DP3-DP0 are active High and are driven during the second and subsequent clocks of write cycles.
CLKMUL
Clock Multiplier (Input) The clock multiplier input defines the ratio of internal core clock frequency to external bus frequency. If sampled Low, the core frequency operates at twice the external bus frequency (speed-double mode). If driven High or left floating speed-triple mode is selected. CLKMUL has an internal pull-up to VCC and may be left floating in designs that wish to select speed-triple clock mode.
EADS
Valid External Address (Active Low; Input) This pin indicates a valid external address has been driven onto the AM486DX4 microprocessor address pins. This address is used to perform an internal cache invalidation cycle. EADS is active Low and is provided with an internal pull-up resistor. EADS must satisfy setup and hold times, t12 and t13, for proper operation.
D31-D0
Data Lines (Inputs/Outputs) Lines D7-D0 define the least significant byte and lines D31-D24 define the most significant byte. These signals must meet setup and hold times t22 and t23 for proper operation on reads. The pins are driven during the second and subsequent write cycle clocks.
FERR
Floating-Point Error (Active Low; Output) Driven active when a floating-point error occurs. FERR is similar to the ERROR pin on a 387 math coprocessor. AM486DX4 Microprocessor 9
AMD
PRELIMINARY
FERR is included for compatibility with systems using DOS-type floating-point error reporting. FERR is active Low, and is not floated during bus hold, except during three-state test mode (see FLUSH).
INTR
Maskable Interrupt (Active High; Input) INTR indicates an external interrupt has been generated. If the internal interrupt flag is set in EFLAGS, active interrupt processing is initiated. The AM486DX4 microprocessor generates two locked interrupt acknowledge bus cycles in response to the INTR pin going active. INTR must remain active until the interrupt acknowledges have been performed. This ensures that the interrupt is recognized. INTR is active High and is not provided with an internal pull-down resistor. INTR is asynchronous, but must meet setup and hold times, t20 and t21, for recognition in any specific clock.
FLUSH
Cache Flush (Active Low; Input) FLUSH forces the AM486DX4 microprocessor to flush its entire internal cache. FLUSH is active Low and need only be asserted for one clock. FLUSH is asynchronous but setup and hold times, t20 and t21, must be met for recognition in any specific clock. FLUSH being sampled Low in the clock before the falling edge of RESET causes the AM486DX4 microprocessor to enter the three-state test mode.
KEN
Cache Enable (Active Low; Input) KEN is used to determine whether the current cycle is cacheable. When the AM486DX4 microprocessor generates a cacheable cycle and KEN is active, the cycle becomes a cache line fill cycle. Returning KEN active one clock before RDY during the last read in the cache line fill causes the line to be placed in the on-chip cache. KEN is active Low and is provided with a small internal pull-up resistor. KEN must satisfy setup and hold times, t14 and t15, for proper operation. LOCK Bus Lock (Active Low; Output) LOCK indicates the current bus cycle is locked. The AM486DX4 microprocessor does not allow a bus hold when LOCK is asserted (but address holds are allowed). LOCK goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when RDY is returned. LOCK is active Low and is not driven during bus hold. Locked read cycles are not transformed into cache fill cycles if KEN is active.
HLDA
Hold Acknowledge (Active High; Output) HLDA goes active in response to a hold request presented on the HOLD pin. HLDA indicates that the AM486DX4 microprocessor has given the bus to another local bus master. HLDA is driven active in the same clock that the AM486DX4 microprocessor floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is active High and remains driven during bus hold. HLDA is never floated except during three-state test mode (see FLUSH).
HOLD
Bus Hold Request (Active High; Input) This input pin allows another bus master complete control of the AM486DX4 microprocessor bus. In response to HOLD going active, the AM486DX4 microprocessor floats most of its output and input/output pins. HLDA is asserted after completing the current bus cycle, burst cycle, or sequence of locked cycles. The AM486DX4 microprocessor remains in this state until HOLD is deasserted. HOLD is active High and is not provided with an internal pull-down resistor. HOLD must satisfy setup and hold times t18 and t19 for proper operation.
NMI
Non-Maskable Interrupt (Active High; Input) A high NMI signal indicates that external non-maskable interrupt occurred. NMI is rising edge sensitive, but must be held Low for at least four-CLK periods before the rising edge. NMI does not have an internal pull-down resistor. NMI is asynchronous, but must meet setup and hold times, t20 and t21, for recognition in any specific clock.
IGNNE
Ignore Numeric Error (Active Low; Input) When this pin is asserted, the AM486DX4 microprocessor will ignore a numeric error and continue executing non-control floating-point instructions. When IGNNE is deasserted, the AM486DX4 microprocessor will freeze on a non-control floating-point instruction if a previous floating-point instruction caused an error. IGNNE has no effect when the NE bit in Control Register 0 is set. IGNNE is active Low and is provided with a small internal pull-up resistor. IGNNE is asynchronous but must meet setup and hold times, t20 and t21, to ensure recognition in any specific clock.
PCD/PWT
Page Cache Disable/Page Write-Through (Active High; Outputs) The outputs reflect the state of the page attribute bits, PWT and PCD, in the page table or page directory entry. If paging is disabled or unpaged cycles occur, PWT and PCD reflect the state of the PWT and PCD bits in Control Register 3. PWT and PCD have the same timing as the cycle definition pins (M/IO, D/C, and W/R). PWT and PCD are active High and are not driven during bus hold. PCD is masked by the Cache Disable Bit (CD) in Control Register 0.
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AM486DX4 Microprocessor
PRELIMINARY
AMD
PCHK
Parity Status (Active Low; Output) Parity status is driven on the PCHK pin the clock after RDY for read operations for data sampled at the end of the previous clock. A parity error is indicated by PCHK being Low. Parity status is only checked for enabled bytes as indicated by the byte enable and bus size signals. PCHK is valid only in the clock immediately after read data is returned to the microprocessor. At all other times PCHK is inactive High. PCHK is never floated except during three-state test mode (see FLUSH).
TCK
Test Clock (Input) Test Clock is an input to the AM486DX4 CPU and provides the clocking function required by the JTAG boundary scan feature. TCK is used to clock state information and data into and out of the component. State select information and data are clocked into the component on the rising edge of TCK on TMS and TDI, respectively. Data is clocked out of the component on the falling edge of TCK on TDO.
TDI
Test Data Input (Input) TDI is the serial input used to shift JTAG instructions and data into the component. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and the SHIFT-DR TAP controller states. During all other tap controller states, TDI is a "don't care."
PLOCK
Pseudo-Lock (Active Low; Output) PLOCK indicates that the current bus transaction requires more than one bus cycle to complete. Examples of such operations are floating-point long reads and writes (64 bits), segment table descriptor reads (64 bits), and cache line fills (128 bits). The AM486DX4 microprocessor drives PLOCK active until the addresses for the last bus cycle of the transaction have been driven, regardless of whether RDY or BRDY has been returned. Normally PLOCK and BLAST are inverse of each other. However, during the first bus cycle of a 64-bit floatingpoint write, both PLOCK and BLAST will be asserted. PLOCK is a function of the BS8, BS16, and KEN inputs. PLOCK should be sampled only if the clock RDY is returned. PLOCK is active Low and is not driven during bus hold.
TDO
Test Data Output (Output) TDO is the serial output used to shift JTAG instructions and data out of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR Test Access Port (TAP) controller states. At all other times, TDO is driven to the high-impedance state.
TMS
Test Mode Select (Input) TMS is decoded by the JTAG TAP to select the operation of the test logic. TMS is sampled on the rising edge of TCK. To guarantee deterministic behavior of the TAP controller, TMS is provided with an internal pull-up resistor.
RESET
Reset (Active High; Input) This pin forces the AM486DX4 microprocessor to begin execution at a known state. The microprocessor cannot begin execution of instructions until at least 1 ms after VCC and CLK have reached their proper DC and AC specifications. The RESET pin should remain active during this time to ensure proper microprocessor operation. RESET is active High. RESET is asynchronous but must meet setup and hold times, t20 and t21, for recognition in any specific clock.
UP
Upgrade Present (Active Low; Input) The Upgrade Present pin forces the AM486DX4 CPU to three-state all its outputs and enter the power-down mode. When the Upgrade Present pin is sampled asserted by the CPU in the clock before the falling edge of RESET, the power-down mode is enabled. UP has no effect on the power-down status except during this edge. The CPU is also forced to three-state all of its outputs immediately in response to this signal. The UP signal must remain asserted in order to keep the pins three-state. UP is active Low and is provided with an internal pull-up resistor.
RDY
Non-Burst Ready (Active Low; Input) This input pin indicates that the current bus cycle is complete. RDY indicates that the external system has presented valid data on the data pins in response to a read, or that the external system has accepted data from the AM486DX4 microprocessor in response to a write. RDY is ignored when the bus is idle and at the end of the bus cycle's first clock. RDY is active during address hold. Data can be returned to the processor while AHOLD is active. RDY is active Low and is not provided with an internal pull-up resistor. RDY must satisfy setup and hold times, t16 and t17, for proper chip operation.
VOLDET
Voltage Detect (Active Low; Output) The voltage detect signal allows external system logic to distinguish between a 5-V Am486 processor and the 3.3-V AM486DX4 processor. The signal is active Low for a 3.3-V AM486DX4 processor.
AM486DX4 Microprocessor
11
AMD Table 3. Output Pins
Name BREQ HLDA BE3-BE0 PCD/PWT W/R, D/C, M/IO LOCK PLOCK ADS BLAST PCHK A3-A2 FERR VOLDET Active Level High High Low High High Low Low Low Low Low High Low Low
PRELIMINARY
Table 5. Input/Output Pins
Name D31--D0 DP3-DP0 A31-A4 Active Level High High High Floated At Bus Hold Bus Hold Bus, Address Hold
Floated At Three-State Test Mode Three-State Test Mode Bus Hold Bus Hold Bus Hold Bus Hold Bus Hold Bus Hold Bus Hold Three-State Test Mode Bus, Address Hold Three-State Test Mode -
Table 6. Test Pins
Name TCK TDI TDO TMS Input or Output Input Input Output Input Sampled/Driven On N/A Rising Edge of TCK Falling Edge of TCK Rising Edge of TCK
Table 4. Input Pins
Name CLK RESET HOLD AHOLD EADS BOFF FLUSH A20M BS16, BS8 KEN RDY BRDY INTR NMI UP IGNNE CLKMUL Active Level - High High High Low Low Low Low Low Low Low Low High High Low Low - Synchronous/ Asynchronous - Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous -
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AM486DX4 Microprocessor
PRELIMINARY
AMD
CPU IDENTIFICATION CODES
The DX register always contains a component identification at the conclusion of RESET. The upper byte of DX (DH) contains 04 and the lower byte of DX (DL) contains a CPU type/stepping identifier. Table 7. CPU ID Component ID (DH)
04
attributes include its location, size, type (i.e., stack, code, or data), and protection characteristics. Each task on an AM486DX4 microprocessor can have a maximum of 16,381 segments, each up to 4 Gbyte in size. Thus, each task has a maximum of 64 Tbyte (terabytes) of virtual memory. The segmentation unit provides four levels of protection for isolating and protecting applications and the operating system from each other. The hardware enforced protection allows high integrity system designs. The AM486DX4 microprocessor has three modes of operation: Real Address Mode (Real Mode), Virtual Address Mode (Protected Mode), and within Protected Mode, tasks may be performed in Virtual 8086 Mode. In Real Mode, the AM486DX4 microprocessor operates as a very fast 8086. Real Mode is required primarily to set up the processor for Protected Mode operation. Protected Mode provides access to the sophisticated memory management paging and privilege capabilities of the processor. Within Protected Mode, software can perform a task switch to enter into tasks designated as Virtual 8086 Mode tasks. Each Virtual 8086 task behaves with 8086 semantics, allowing 8086 software (an application program or an entire operating system) to execute. The on-chip cache is 8 Kbyte. It is four-way set associative and follows a write-through policy. The on-chip cache includes features that provide flexibility in external memory system design. Individual pages can be designated as cacheable or non-cacheable by software or hardware. The cache can also be enabled and disabled by software or hardware. Finally, the AM486DX4 microprocessor has features that facilitate high-performance hardware designs. The clock multiplier improves execution performance without increasing the board design complexity. This clock multiplier enhances all operations operating out of the cache and/or not blocked by external bus assesses. The burst bus feature enables fast cache fills.
Component ID (DL)
32
Table 8. JTAG ID Code Version Code
00h
Part Number Code
0432
Manufacturer Identity
01
ARCHITECTURAL OVERVIEW
The AM486DX4 processor is a 32-bit architecture with on-chip memory management and cache memory units. It is a fully compatible member of the Am486 Family. On-chip cache memory allows frequently used data and code to be stored on-chip, thereby reducing accesses to the external bus. A clock multiplier has been added to speed up internal operations. RISC design techniques are used to reduce instruction cycle times. A burst bus feature enables fast cache fills. The Am486 CPU Memory Management Unit (MMU) consists of a segmentation unit and a paging unit. Segmentation allows management of the logical address space by providing easy data and code relocatibility and efficient sharing of global resources. The paging mechanism operates beneath segmentation and is transparent to the segmentation process. Paging is optional and can be disabled by system software. Each segment can be divided into one or more 4-Kbyte segments. To implement a virtual memory system, the AM486DX4 microprocessor supports full restartability for all page and segment faults. Memory is organized into one or more variable length segments, each up to 4 Gbyte (232 bytes) in size. A segment can have attributes associated with it. These
AM486DX4 Microprocessor
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ELECTRICAL DATA
The following sections describe recommended electrical connections for the AM486DX4 microprocessor and its electrical specifications. Low inductance capacitors and interconnects are recommended for best high-frequency electrical performance. Inductance can be reduced by shortening circuit board traces between the AM486DX4 CPU, and decoupling capacitors as much as possible. Capacitors specifically for PGA packages are also commercially available. System Clock Recommendations The CLK input to the AM486DX4 processor should not be driven until VCC has reached its normal operating level (3.3 V). Once VCC has reached its normal operating level, the AM486DX4 CPU can handle the clock frequency for which it is specified and the oscillator/clock driver should have locked onto its desired frequency. Other Connection Recommendations NC pins should always remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Active Low inputs should be connected to VCC through a pull-up resistor. Pull-ups in the range of 20 K are recommended. Active High inputs should be connected to GND. INC is electrically isolated and has no special requirements.
Power and Grounding
Power Connections The AM486DX4 CPU is implemented in 0.5 micron CMOS 3-layer metal technology and has modest power requirements. However, its high clock frequency output buffers can cause power surges as multiple output buffers drive new signal levels simultaneously. For clean, on-chip power distribution at high frequency, 23 VCC and 28 VSS pins feed the AM486DX4 microprocessor. Power and ground connections must be made to all external VCC and GND pins of the AM486DX4 microprocessor. On the circuit board, all VCC pins must be connected on a VCC plane. All VSS pins must likewise be connected on a GND plane. Power Decoupling Recommendations Liberal decoupling capacitance should be placed near the AM486DX4 microprocessor. The AM486DX4 microprocessor, driving its 32-bit parallel address and data buses at high frequencies, can cause transient power surges, particularly when driving large capacitive loads.
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PRELIMINARY
AMD
ABSOLUTE MAXIMUM RATINGS
Case Temperature under Bias .......... -65C to +110C Storage Temperature ........................ -65C to +150C Voltage on any pin with respect to ground ............-0.5 V to VCC +2.6 V Supply voltage with respect to VSS................................ -0.5 V to +4.6 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices TCASE ....................................................... 0C to +85C VCC .......................................................... 3.3 V 0.3 V
Operating Ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges
Functional Operating Range: VCC= 3.3 V 0.3 V; TCASE =0C to +85C. Preliminary
Symbol VIL VIH VOL VOH ICC ILI IIH IIL ILO CIN COUT CCLK Parameter Description Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Power Supply Current Input Leakage Current Input Leakage Current Input Leakage Current Output Leakage Current Input Capacitance I/O or Output Capacitance CLK Capacitance IOL =(Note 1) IOH =(Note 2) 100 MHz (Note 3) 120 MHz (Note 3) (Note 4) (Note 8) (Note 5) (Note 6) (Note 9) (Note 10) FC =1 MHz (Note 7) FC =1 MHz (Note 7) FC =1 MHz (Note 7) 2.4 1000 1200 15 50 200 -400 15 50 10 14 12 Notes Min -0.3 2.0 Max +0.8 VCC +2.4 0.45 Unit V V V V mA A A A A pF pF pF
Notes: 1. This parameter is measured at:
Address, Data, BE3-BE0 4.0 mA Definition, Control 5.0 mA 2. This parameter is measured at: Address, Data, BE3-BE0 -1.0 mA Definition, Control -0.9 mA 3. Typical supply current: 800 mA @ 100 MHz or 960 mA @ 120 MHz 4. This parameter is for inputs without pull-ups or pull-downs and 0 VIN VCC. 5. This parameter is for inputs with pull-downs and VIH =2.4 V. 6. This parameter is for inputs with pull-ups and VIL =0.45 V. 7. Not 100% tested. 8. This parameter is for inputs without pull-ups or pull-downs and VCC VIN 5V. 9. This parameter is for three-state outputs where VEXT is driven on the three-state output and 0 VEXT VCC. 10. This parameter is for three-state outputs where VEXT is driven on the three-state output and VCC VEXT 5V.
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AMD
PRELIMINARY
SWITCHING CHARACTERISTICS
The switching characteristics consist of output delays, input setup requirements, and input hold requirements. All switching characteristics are relative to the rising edge of the CLK signal. The switching characteristics measurements are defined by Figures 2-9. Inputs must be driven to the voltage levels indicated by Figure 2 when switching characteristics are measured. AM486DX4 microprocessor output delays are specified with minimum and maximum limits. The minimum AM486DX4 microprocessor delay times are hold times provided to external circuitry. AM486DX4 microprocessor input setup and hold times are specified as minimums, defining the smallest acceptable sampling windows. Within the sampling windows, a synchronous input signal must be stable for correct AM486DX4 microprocessor operation.
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AM486DX4 Microprocessor
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Operating Frequency/Bus Frequency: 120/40MHz; TCASE =0C to +85C; CL =50 pF unless otherwise specified.
Preliminary
Symbol Parameter Description Operating Frequency t1 t1a t2 t3 t4 t5 t6 CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time A31-A2, PWT, PCD, M/IO, BE3-BE0, D/C, W/R, ADS, LOCK, FERR, BREQ, HLDA Valid Delay A31-A2, PWT, PCD, M/IO, BE3-BE0, D/C, W/R, ADS, LOCK, FERR, BREQ, HLDA Float Delay PCHK Valid Delay BLAST, PLOCK Valid Delay BLAST, PLOCK Float Delay D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS Setup Time EADS Hold Time KEN, BS16, BS8 Setup Time KEN, BS16, BS8 Hold Time RDY, BRDY Setup Time RDY, BRDY Hold Time HOLD, AHOLD Setup Time BOFF Setup Time HOLD, AHOLD, BOFF Hold Time RESET, FLUSH, A20M, NMI, INTR, IGNNE Setup Time RESET, FLUSH, A20M, NMI, INTR, IGNNE Hold Time D31-D0, DP3-DP0, A31-A4 Read Setup Time D31-D0, DP3-DP0, A31-A4 Read Hold Time (Note 1) (Note 1) (Note 1) Adjacent Clocks @ 2.0 V @ 0.8 V 2 2 2 2 7 3 9 9 3 3 14 2 Notes Figure Min 8 25 Max 40 125 0.1% Unit MHz ns ns ns ns ns ns
t7
8
3
18
ns
t8 t8a t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t18a t19 t20 t21 t22 t23
6 7 8 7 8 4 4 4 4 5 5 4 4 4 3, 4 3, 4 4, 5 4, 5
3 3 3 3 3 5 3 5 3 5 3 6 8 3 5 3 5 3
16 18 16 16 18
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Not 100% tested. Guaranteed by design characterization.
AM486DX4 Microprocessor
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AMD
PRELIMINARY
Operating Frequency/Bus Frequency: 100/33 MHz; TCASE =0C to +85C; CL =50 pF unless otherwise specified. Preliminary Symbol Parameter Description Operating Frequency t1 t1a t2 t3 t4 t5 t6 CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time A31-A2, PWT, PCD, M/IO, BE3-BE0, D/C, W/R, ADS, LOCK, FERR, BREQ, HLDA Valid Delay A31-A2, PWT, PCD, M/IO, BE3-BE0, D/C, W/R, ADS, LOCK, FERR, BREQ, HLDA Float Delay PCHK Valid Delay BLAST, PLOCK Valid Delay BLAST, PLOCK Float Delay D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS Setup Time EADS Hold Time KEN, BS16, BS8 Setup Time KEN, BS16, BS8 Hold Time RDY, BRDY Setup Time RDY, BRDY Hold Time HOLD, AHOLD Setup Time BOFF Setup Time HOLD, AHOLD, BOFF Hold Time RESET, FLUSH, A20M, NMI, INTR, IGNNE Setup Time RESET, FLUSH, A20M, NMI, INTR, IGNNE Hold Time D31-D0, DP3-DP0, A31-A4 Read Setup Time D31-D0, DP3-DP0, A31-A4 Read Hold Time (Note 1) (Note 1) (Note 1) Adjacent Clocks @ 2.0 V @ 0.8 V 2 2 2 2 7 3 11 11 3 3 14 2 Notes Figure Min 8 30 Max 33 125.5 0.1% Unit MHz ns ns ns ns ns ns
t7
8
20
ns
t8 t8a t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t18a t19 t20 t21 t22 t23
6 7 8 7 8 4 4 4 4 5 5 4 4 4 3, 4 3, 4 4, 5 4, 5
3 3
14 14 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3
14 20
5 3 5 3 5 3 6 7 3 5 3 5 3
Note: 1. Not 100% tested. Guaranteed by design characterization.
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AM486DX4 Microprocessor
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AM486DX4 CPU AC Characteristics for Boundary Scan Test Signals at 25 MHz
VCC = 3.3 V 0.3 V; TCASE =0C to +85C; CL = 50 pF. All inputs and outputs are TTL Level.
Symbol t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 Parameter TCK Frequency TCK Period TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Outputs (Non-Test) Valid Delay All Outputs (Non-Test) Float Delay All Inputs (Non-Test) Setup Time All Inputs (Non-Test) Hold Time 8 7 3 8 7 3 25 30 25 36 40 10 10 4 4 Min Max 25 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 9 9 9 9 9 Figure Notes 1X Clock Note 2 at 2.0 V at 0.8 V Note 1 Note 1 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3
Notes: 1. Rise/Fall times are measured between 0.8 V and 2.0 V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK period. 2. TCK period > CLK period. 3. Parameter measured from TCK.
AM486DX4 Microprocessor
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AMD
PRELIMINARY
WAVEFORM
INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply
OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS00000
Figure 1. Change State Diagram
t2 2.0 V 1.5 V 0.8 V t5 t1 t4 t3
17852B-095
Figure 2. CLK Waveforms
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AM486DX4 Microprocessor
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AMD
RESET
Initialization Sequence
Tx
CLK
Tx
Tx
Tx
t20
RESET
t21
19160c.003
Figure 3. Reset Setup and Hold Timing
Tx CLK
Tx
Tx
Tx
t12
EADS
t13
t14
BS8, BS16, KEN
t15
t18a
BOFF, AHOLD, HOLD RESET, FLUSH, A20M, IGNNE, INTR, NMI
t19 t21
t20
t22
A31-A4 (Read)
t23
19160c.004
Figure 4. Input Setup and Hold Timing
AM486DX4 Microprocessor
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AMD
PRELIMINARY
T2 CLK t16 RDY, BRDY
Tx
Tx
Tx
t17 1.5 V
D31-D0 DP3-DP0 (Read)
t22
t23 1.5 V
19160c.005
Figure 5. RDY and BRDY Input Setup and Hold Timing
T2 CLK
Tx
Tx
Tx
BRDY, RDY
D31-D0 DP3-DP0 (Read) t8 PCHK
Valid
Min Max
Valid
19160c.006
Figure 6. PCHK Valid Delay Timing
Tx CLK Tx Tx Tx
A31-A2, PWT, PCD, BE3-BE0, M/IO, D/C, W/R, ADS, LOCK, FERR, BREQ, HLDA
t6
Valid n
Min
Max Valid n +1
t10
D31-D0, DP3-DP0, (Write)
Valid n
Min
Max Valid n +1
t8a
BLAST, PLOCK
Valid n
Min
Max Valid n +1
19160c.007
Figure 7. Output Valid Delay Timing
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AM486DX4 Microprocessor
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AMD
Tx CLK
Min
Tx
Tx
Tx
A31-A2, PWT, PCD, BE3-BE0, M/IO, D/C, W/R, ADS, LOCK, FERR, BREQ, HLDA
t6
Valid
t7
t10
D31-D0, DP3-DP0 (Write)
Valid
Min
t11
Min
t8a
BLAST, PLOCK
Valid
t9
17852A-103
Figure 8. Maximum Float Delay Timing
t25
TCK
t30
TDI, TMS
t31
t33
t32
TDO Output Signals Input Signals
t35 t34 t36 t37
17852B-104
Figure 9. Test Signal Timing Diagram
AM486DX4 Microprocessor
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AMD
PRELIMINARY where: TJ, TA, TCASE= Junction, Ambient, and Case Temperature. JC, JA = Junction-to-Case and Junction-to-Ambient Thermal Resistance, respectively. P = Maximum Power Consumption The values for JA and JC are given in Table 9 for the 1.75 sq. in., 168-pin, ceramic PGA.
Package Thermal Specifications
The AM486DX4 microprocessor is specified for operation when TCASE (the case temperature) is within the range of 0C to +85C. TCASE can be measured in any environment to determine whether the AM486DX4 microprocessor is within specified operating range. The case temperature should be measured at the center of the top surface opposite the pins. The ambient temperature (TA) is guaranteed as long as TCASE is not violated. The ambient temperature can be calculated from JC and JA and from the following equations:
Table 10 shows the TA allowable (without exceeding TCASE) at various airflows and operating frequencies (Clock). Note that TA is greatly improved by attaching TJ = TCASE + P * JC fins or a heat sink to the package. Heat sink dimensions are shown in Figure 10. P (the maximum power TA = TJ - P * JA consumption) is calculated by using the maximum ICC at 3.3 V as tabulated in the DC Characteristics. TCASE = TA + P * [JA - JC] ---------------------------------------------------------------------------------------------------------------------------- Table 9. Thermal Resistance (C/W) JC and JA for the 168-Pin, Ceramic PGA Package
JC No Heat Sink Heat Sink* Heat Sink* and fan 1.5 2.0 2.0 JA vs. Airflow-ft/min. (m/sec) 0 (0) 16.5 12.0 5.0 200 (1.01) 14.0 7.0 4.6 400 (2.03) 12.0 5.0 4.2 600 (3.04) 10.5 4.0 3.8 800 (4.06) 9.5 3.5 3.5 1000 (5.07) 9.0 3.25 3.25
*0.350 high unidirectional heat sink (Al alloy 6063-T5, 40 mil fin width, 155 mil center-to-center fin spacing). 0.115 0.040
0.290 0.060 0.350 0.100 1.53
17852B-113
Figure 10. Heat Sink Dimensions Table 10. Maximum TA at Various Airflows in C
Clock TA--No Heat Sink TA--Heat Sink TA--Heat Sink and fan 100 MHz 100 MHz 120 MHz 100 MHz 120 MHz Airflow-ft/min. (m/sec) 0 (0) 31.0 49.0 41.8 74.2 72.0 200 (1.01) 41.8 67.0 63.4 75.6 73.8 400 (2.03) 49.0 74.2 72.0 77.1 75.5 600 (3.04) 54.4 77.8 76.4 78.5 77.2 800 (4.06) 58.0 79.6 78.5 79.6 78.5 1000 (5.07) 59.8 80.5 79.6 80.5 79.6
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AM486DX4 Microprocessor
PRELIMINARY
AMD
PHYSICAL DIMENSIONS
For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering. CGM 168
1.735 1.765 1.595 1.605
Index Corner
Base Plane Seating Plane
1.595 1.605
0.017 0.020
1.735 1.765
0.090 0.110
0.105 0.125 0.140 0.180 0.110 0.140
Bottom View (Pins Facing Up)
0.025 0.045
Side View
16734C 5/11/93 MH
AMD, Am386, and Am486 are registered trademarks of Advanced Micro Devices, Inc. FusionPC is a service mark of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corp. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
AM486DX4 Microprocessor
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AMD
PRELIMINARY
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AM486DX4 Microprocessor

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